This invention relates generally to power MOS field-effect devices, which includes power MOSFETs, insulated gate bipolar transistors (IGBT), MOS controlled thyristors and the like, and more particularly to recessed gate, rectangular-grooved or U-grooved power MOS field effect devices, commonly referred to as RMOSFETs or UMOSFETs.
Power MOSFETs have been recognized as provided a number of advantages over power bipolar transistors, particularly in regard to fast switching response, high input impedance and high thermal stability. A major disadvantage of power MOSFETs is their large ON-resistance and forward voltage drop compared to bipolar transistors. Significant efforts have gone into reducing the ON-resistance per unit area. These efforts include reducing the cell size of the devices to increase cell density, but the ability to do this in conventional VDMOS devices is limited by the presence of a parasitic junction FET between adjacent cells which increases ON-resistance as the device structure is scaled to smaller cell sizes. K. Shenai, "Optimally Scaled Low-Voltage Vertical Power MOSFET's for High Frequency Power Conversion," IEEE Trans. On Electron Devices, Vol. 37, No. 2, April, 1990 describes how the VDMOS device structure, having the gate and channel extending horizontally along the top surface of the semiconductor substrate, is inherently limited in density, necessitating other measures to reduce ON-resistance.
To avoid this inherent limitation, another class of power MOS field-effect devices has been developed using a recessed gate, in which the gate and channel are formed vertically along a sidewall of a channel or trench etched in the semiconductor substrate. These devices include rectangular-grooved or U-grooved power MOS field effect devices, commonly referred to as RMOSFETs or UMOSFETs. An early device of this type appears in U.S. Pat. No. 4,070,690 to Wickstrom. The source, channel and drain are formed by successive layers deposited on a substrate and trenched through for gate oxide formation and gate metal deposition on sidewalls of the trench. A variation of this approach, called the VMOS, is shown in U.S. Pat. No. 4,145,703 to Blanchard et al. Subsequently, it was recognized that the vertical channel orientation in this type of device could be scaled down to increase cell density without parasitic junction FET effects and thereby reduce ON-resistance below the inherent limitations of VDMOS devices. (See D. Ueda et al., "A New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance," IEEE Trans. on Electron Devices, Vol. 32, No. 1, January, 1985) Further development of recessed gate technology is summarized below based on references listed at the end of the detailed description.
The usual starting material is a N+ wafer with a &lt;100&gt; oriented N epitaxial layer of a resistivity and thickness in the ranges of 0.1-1.0 ohm-cm and 5-10 .mu.m for low voltage MOSFETs to achieve a breakdown voltage of 15-55 V using rectangular striped grooves. This voltage range can be changed by adjusting untrenched P-base width, trench depth and width, and epi-layer doping. The N+ substrate can be replaced by a P+ substrate to make IGBTs as in DMOS technology.
A blanket P-type implant into the top surface of the epitaxial layer is diffused to 1.5-2.0 .mu.m depth to form a P-type body region. A first mask can be used at this stage to define N+ source regions.
An oxide layer is thermally grown and a trenching protective layer of silicon nitride (or LPCVD oxide, polysilicon/silicon nitride/oxide or other layer resistant to Si etching) is deposited to protect P-body/N-source regions from trenching.
Regions to be trenched are exposed during photomasking, at right angles to the source regions if they have been defined previously, and the trenching protective layer is defined. Reactive ion etching (RIE) is then used to form the gate trenches, typically to a depth of 2 .mu.m but variable as discussed below. Reactive ion etching can damage the substrate surface, causing high surface charge and low surface mobility. Chemical etching and sacrificial oxidation/etching steps are typically performed to restore surface mobility and channel conductance.
Gate oxide of 500-2000 .ANG. is regrown in the trench, and .about.6000 .ANG. thick polysilicon is deposited in the trench and doped to a sheet resistance of about 20 ohm/.quadrature.. A second polysilicon layer is deposited to planarize the surface and etched back to open the trenching protective layer. The trenching protective layer can be used in a self-aligned LOCOS (LOcalized Oxidation of Silicon) step to selectively oxidize and isolate the polysilicon gate structures from the P-body/N-source regions. The maximum LOCOS film thickness is limited by minimum linewidth because of "birds beak" sidewall oxidation encroachment. With a 2 .mu.m/2 .mu.m minimum gate/source design rule, this layer cannot be much greater than 1 .mu.m thick or the source region will be completely sealed off by LOCOS encroachment. The LOCOS process further induces stress immediately surrounding the selective oxidation zone, wherein the MOS channel is formed, reducing surface mobility and increasing channel resistance.
If the source region has not already been defined, another photomasking step is performed to introduce the N-type source regions into the P-body contact regions, usually with a striped geometry perpendicular to the trench sidewalls, to effect distinctive P and N dopings at the top surface of the silicon, to short the P-body to the N+ source regions (10). This technique produces pinched P-base regions which are of wide dimensions, typically 2 .mu.m or more, and must be meticulously controlled in the photolithographic process. This step causes loss of channel width wherever N+ source is absent and reduces device ruggedness.
In one approach (2, 5, 10-FIG. 10), to improve packing density and more tightly control the lateral extent of the pinched B-base and avoid photolithographic control, lateral N+ diffusions are made from the windows formed in the trenching protective layer prior to trenching. In this approach, the P and N+ diffusions are fully diffused before gate oxidation, without partitioning the respective diffusion times to allow part of the diffusion cycles to be used for annealing RIE- and LOCOS-induced surface stress and defects. Also in this approach, contacts are made on lighter doped N+ diffusions, increasing series resistance of the device. A tradeoff is required between pinched base resistance and source contact resistance. There is a lower limit to how small the lateral diffusions can be made and consistently opened up after the LOCOS gate polysilicon oxidation due to "birds beak" formation. A dimension anywhere between 50% and 80% of the polysilicon LOCOS oxide thickness may not be available for a source contact of highest doping.
Another approach is to form a second trench through the N-source layer down to the P-body to receive source metal. This trench can be patterned by a separate photomasking step (1) but this approach is subject to critical alignment and size conditions. A self-aligned approach (11) depends on the ability to control both formation of the LOCOS oxide layer used to self-align this trenching step and to control the etching process itself. As noted above, "birds beak" formation can seal off the area to be trenched.
Once the basic recessed gate structure is formed, gate vias are opened to allow metal connections to the gate electrode in a self-aligned process. Frontside metal is deposited and patterned to delineate the gate and source (cathode) electrodes. Passivation deposition and pad patterning seal the device surface and open up the bonding pads. The backside of the silicon wafer is metallized to form the drain (anode) electrode.
Ueda et al have demonstrated that the lowest ON-resistance (R.sub.ON) is achievable in a device in which the gate is trenched all the way through the N-epitaxial layer to the substrate (2). Unfortunately this approach also demonstrates a monotonic decrease in breakdown voltage as trench depth is increased. This decrease is due to reduction of the epi-layer thickness below the trench and higher electric field at the corners of the trench (7). Another problem with the deep trench is that the gate oxide might rupture at the corner of the trench because of high field intensity (7). The breakdown voltage is generally divided between gate oxides and depleted silicon. As trench depth is increased, the thickness of silicon under the trench is reduced, shifting more of the gate-drain voltage to the gate oxide and increasing the likelihood that the oxide layer will rupture. Thickening the gate oxide will improve the gate rupture resistance of the oxide layer but also increases channel resistance.
Accordingly, a need remains for a better fabrication method and structure for a vertical channel field effect MOS power device.